Several types of memory devices, such as Flash memories, use arrays of analog memory cells for storing data. Each analog memory cell stores a quantity of an analog value, such as an electrical charge or voltage, which represents the information stored in the cell. In Flash memories, for example, each analog memory cell holds a certain amount of electrical charge. The range of possible analog values is typically divided into regions, each region corresponding to one or more data bit values. Data is written to an analog memory cell by writing a nominal analog value that corresponds to the desired bit or bits.
Some memory devices, commonly referred to as Single-Level Cell (SLC) devices, store a single bit of information in each memory cell, i.e., each memory cell can be programmed to assume two possible memory states. Higher-density devices, often referred to as Multi-Level Cell (MLC) devices, store two or more bits per memory cell, i.e., can be programmed to assume more than two possible memory states.
Flash memory devices are described, for example, by Bez et al., in “Introduction to Flash Memory,” Proceedings of the IEEE, volume 91, number 4, April, 2003, pages 489-502, which is incorporated herein by reference. Multi-level Flash cells and devices are described, for example, by Eitan et al., in “Multilevel Flash Cells and their Trade-Offs,” Proceedings of the 1996 IEEE International Electron Devices Meeting (IEDM), New York, N.Y., pages 169-172, which is incorporated herein by reference. The paper compares several kinds of multilevel Flash cells, such as common ground, DINOR, AND, NOR and NAND cells.
Eitan et al., describe another type of analog memory cell called Nitride Read Only Memory (NROM) in “Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?” Proceedings of the 1999 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, Sep. 21-24, 1999, pages 522-524, which is incorporated herein by reference. NROM cells are also described by Maayan et al., in “A 512 Mb NROM Flash Data Storage Memory with 8 MB/s Data Rate”, Proceedings of the 2002 IEEE International Solid-State Circuits Conference (ISSCC 2002), San Francisco, Calif., Feb. 3-7, 2002, pages 100-101, which is incorporated herein by reference. Other exemplary types of analog memory cells are Floating Gate (FG) cells, Ferroelectric RAM (FRAM) cells, magnetic RAM (MRAM) cells, Charge Trap Flash (CTF) and phase change RAM (PRAM, also referred to as Phase Change Memory—PCM) cells. FRAM, MRAM and PRAM cells are described, for example, by Kim and Koh in “Future Memory Technology including Emerging New Memories,” Proceedings of the 24th International Conference on Microelectronics (MIEL), Nis, Serbia and Montenegro, May 16-19, 2004, volume 1, pages 377-384, which is incorporated herein by reference.
Several methods and systems are known in the art for determining the voltages, which are used for programming analog memory cells. For example, U.S. Pat. No. 6,301,151, whose disclosure is incorporated herein by reference, describes a programming method in which the voltage of a programming pulse is adjusted based on the result of a previous pulse. The expected change in the programmed value of a cell is compared to the measured change, and the difference used to improve the model of the cell after each programming pulse. U.S. Patent Application Publication 2007/0058446, whose disclosure is incorporated herein by reference, describes methods for erasing and programming Flash memory devices, in which some of the cells are pre-programmed so as to reduce a voltage range in which threshold voltages are distributed.
U.S. Patent Application Publication 2007/0159889, whose disclosure is incorporated herein by reference, describes a method for programming a Flash memory device, which includes a plurality of memory cells for storing multi-bit data. Memory cells that are programmed within a predetermined region of a threshold voltage distribution are detected. The predetermined region is selected by one of a first verify voltage and a read voltage and a second voltage. The first verify voltage is lower than the second verify voltage and higher than the read voltage. The detected memory cells are programmed to have a threshold voltage that is equivalent to or higher than the second verify voltage corresponding to each of the states.
U.S. Pat. No. 7,130,210, whose disclosure is incorporated herein by reference, describes methods for programming a word line of multi-level Flash memory cells having three or more data levels per bit corresponding to three or more threshold voltages. An interactive programming algorithm programs the bits of the word line in two programming phases, a rough programming phase and a fine programming phase, so as to achieve compact threshold voltage distributions.
U.S. Patent Application Publication 2007/0183210, whose disclosure is incorporated herein by reference, describes a method for programming a Flash memory device, which includes a plurality of memory cells for storing multi-bit data indicating one of a plurality of states. The memory cells are subjected to a primary program operation. Those memory cells arranged within a specific region of respective states are subjected to a secondary program operation to have a threshold voltage equivalent to or higher than a verify voltage used in the primary program operation. Thus, although the threshold voltage distribution may be widened, a read margin between adjacent states may be sufficiently secured using the program method.